Current semiconductor design practices often require extensive simulation of semiconductor designs, particularly analog-based designs, at or beyond 3 sigma. Scan-based, or other functional-based tests, which are typically the only types of tests that are used to disposition semiconductor products (i.e., determining whether products meet pass/fail criteria), typically do not identify parametric sensitivities for semiconductor designs, so in many cases not all functional process corners will be completely tested, which can increase the risk that defective products may be inadvertently shipped to customers. Parametric sensitivities relate, for example, to a number of different electrical or physical parameters (e.g., FET currents or threshold voltages, channel length, oxide thickness, resistance, capacitance) that can vary over a distribution as a result of variations in a fabrication process, and that can affect the likelihood that a particular manufactured semiconductor product will function correctly and within spec.
Conventionally, a large amount of resources are required to ensure that a semiconductor product design functions at the corners of parametric distributions (i.e., at the extremes of acceptable parametric distributions). However, there is typically a relatively low probability that a product will actually be manufactured near the corners of a distribution. As a result, semiconductor product designs are often designed overly conservatively, resulting in lost performance or excessively large designs just to account for the relatively low possibility that the resulting products will not meet spec. Otherwise, extended design and simulation time are required to ensure that a product design is fully functional at all possible parametric corners.
Therefore, a substantial need exists in the art for a manner or methodology for designing and testing semiconductor products that appropriately accounts for parametric sensitivities within a semiconductor product design and allows trade-off between yield loss and design optimization.